1. Field of the Invention
The invention relates to the packaging of chips to enable proximity communication, and in particular, to the need for proper alignment (in x-, y-, and z-directions) in a thermally and mechanically challenging environment surrounding the chip.
2. Background Art
High performance computing (HPC) has entered into the multi-core CPU era. Although the computational bandwidth may scale linearly with the number of cores, the communication bandwidth between multiple cores on multiple chips is becoming a potential system bottleneck. Proximity Communication (PxC) holds the promise of revolutionizing HPC by solving its communication bottleneck. Proximity communication can be broadly defined as wireless electromagnetic communication between chips, and has been investigated by means of capacitive coupling, inductive coupling, and most recently, optical coupling between chips.
In capacitive coupling, typically, square or rectangular pads are used on both chips. Binary voltages are applied to the transmitter plate that in turn induce corresponding voltage changes in the receiving pad. One of the critical issues of proximity communication is a need for proper alignment (in x-, y-, and z-directions) in a thermally and mechanically challenging environment surrounding the chip.
FIG. 1 depicts the general concept for face-to-face integrated circuits communicating by capacitive or optical methods—proximity communication. In both cases, very high communication signal density can be achieved when compared to wire-bonding or solder-ball connections. In addition, to communicate off-chip, the circuits need drive only a high-impedance, capacitive pad (or optical modulator), very much akin to the gate of a transistor. This removes the need for high-to-low impedance converters that have traditionally prevented substantive reduction in the power dissipation of the off-chip driver circuits in spite of improvements in transistor efficiency.
As shown in FIG. 1, an array 10 of silicon chips 12, 14 is illustrated. The silicon chips 12, 14 are positioned face-to-face with overlapping areas 16 exchanging electromagnetic signals via capacitive or optical proximity communication. The triangular symbol 18 points to the active surface of the chip or wafer.
In the capacitive case, the electrical pad pitch may be on the order of 20 microns. Each pad can drive signals at line rates of 2.5-5 Gbps or higher. This provides a potential communication density in excess of 1.25 petabits/cm2. Experimental capacitive proximity communication circuits have yielded aerial densities up to 43 terabits/cm2 to date. In the optical case, an optical coupler can be as small as 20 microns on a side. The optical coupler may communicate many wavelength-multiplexed channels (for example, as few as four or as many as 64 may be envisaged with current technologies), with each channel operating at line rates of 10 Gbps and larger. The assumption of 16 channels at 10 Gbps per channel with an optical coupler pitch of 35 microns results in a potential communication density of 13 petabits/cm2.
With continuing reference to FIG. 1, it is useful to connote the lower chips 14 in FIG. 1 as “island” chips, and the upper chips 12 as “bridge” chips. Hence, power and ground may be externally provided to the island chips 14, which may additionally have much greater functionality, processing power, and consequently power consumption. The bridge chips 12 may have correspondingly lower functionality and power consumption with their primary function being to connect two or more island chips 14 together. In this configuration, electrical power and cooling must separately be supplied to the exterior surface of each chip layer. The challenge is doing this in a manner which will provide the required alignment between chips. This challenge gets significantly greater as the power levels of the chips and the number of chips increase.
In addition to the lateral tolerance, there is a need to maintain the vertical “z-separation” between corresponding transmitter and receiver pads on opposing chips to a minimum. This is because the capacitively coupled signal voltage on a particular receiver pad is inversely proportional to the distance between the receiver pad and the transmitter pad located on the opposing chip. The maintenance of this precise z-alignment is difficult, particularly as the number of chips in the array grows large. An additional factor that makes this alignment difficult is that such an array may experience large temperature excursions and temperature gradients during operation. As described above, the island chips 14 and corresponding bridge chips 12 will require precision alignment not only laterally but also axially (in other words z-direction or height), to enable signals to be reliably transferred between chips using proximity communication.
It is typically the case that the vertical separation between facing chips must be maintained below a cut-off distance at which point the capacitive coupling between chips is insufficiently strong to support reliable communication channels between the chips. Hence, when the bridge chips 12 and island chips 14 are rigid (that is, non-compliant), the alignment of a large array of chips becomes challenging. This is especially true when taking into account the flatness tolerances of the heat-sink or the supporting base of the chip arrays in the package and packaging considerations associated with tiling chips in a remateable fashion.
Existing approaches for packaged multi-chip proximity communication must permit the use of juxtaposed semiconductor chips that both face down and face up in the same package—resulting in increased package complexity and cost.
Background information may be found in Robert J. Drost, Robert David Hopkins, Ron Ho, Ivan E. Sutherland, “Proximity Communication,” IEEE Journal of Solid-State Circuits, vol. 39, no. 9, September 2004, pp. 1529-1535; Alex Z. Kattamis, Russell J. Holmes, I-Chun Cheng, Ke Long, James C. Sturm, Stephen R. Forrest, and Sigurd Wagner, “High Mobility Nanocrystalline Silicon Transistors on Clear Plastic Substrates,” IEEE Electron Device Letters, vol. 27, no. 1, January 2006, pp. 49-51; K. Long, A. Z. Kattamis, I.-C. Cheng, H. Gleskova, S. Wagner, and J. C. Sturm, “Stability of Amorphous-Silicon TFTs Deposited on Clear Plastic Substrates at 250° C. to 280° C.,” IEEE Electron Device Letters, vol. 27, no. 2, February 2006, pp. 111-113; Sung Kyu Park, Sankar Subramanian, John Anthony, and Thomas N. Jackson, “Solution processed OTFT circuits on plastic substrates,” IEEE, 2007.
Further background information may be found in U.S. Pat. Nos. 7,592,707, 7,574,077, 7,554,195, 7,514,289, 7,486,853, and 7,356,213. Further background information may also be found in U.S. Pub. Nos. 2009/0280601, 2009/0179334, 2009/0089466, 2009/0085233, 2009/0085183, 2009/0067851, 2007/0216036, 2007/0152344, 2007/0075444, 2007/0075443, 2007/0075442, and 2006/0095639.